Definition of RISC and CISC ARCHITECTURE and their difference | Computer science fundamentals tutorial

RISC (Reduced Instruction set computer) AND CISC(Complex instruction set computer) ARCHITECTURE

RISC(Reduced Instruction set computer): -

Main idea behind is to make hardware simpler by using an instruction set composed of a few basic steps for loading, evaluating and storing operation just like load command will load data, store command will store data.

Characteristic of RISC architecture:-

1. Simpler instructions, hence simple instruction decoding.

2. Instruction come under size of one word.

3. Instruction take single clock cycle to get executed.

4. More number of general purpose register.

5. Simple addressing mode.

6. Less data type.

7. Pipelining can be achieved.

CISC(Complex instruction set computer): -

Main idea is to make hardware complex as a single instruction will do all loading evaluating and storing operation just like a multiplication command will do stuff like loading data, evaluating and storing it.

Characteristic of CISC architecture: - 

1. Complex instruction  hence complex instruction decoding.

2. Instruction are larger than one word size.

3. Instruction may take more than single clock cycle to get executed.

4. Less number of general purpose register as operation get performed in memory itself.

5. Complex addressing mode.

6. More data type.

** NOTE**

Both approaches try to increase CPU performance. RISC reduce the cycle per instruction at the cost of increase in the number of  instruction and CISC approach attempt the minimize the number of instruction per program but at the cost of increase in the number of cycle per instruction.

Comparison between RISC(Reduced Instruction set computer) and CISC(Complex instruction set computer)

Characteristic	RISC(Reduced Instruction set computer)	CISC(Complex instruction set computer)
Instruction set size and instruction format	1. Instruction set is small and format is fixed.	1. Instruction set is very large and instruction format is variable 16 to 64 bit per instruction.
Addressing mode	2. Addressing mode of RISC is between 3 to 5	2. Addressing mode of CISC is between 12 to 24.
CPI( Cycle per instruction)	3. In more cases is 1 but average CPI is 1.5.	3. CPI is between 2- 15.
CPU control	4. CPU is control by hardware without control memory.	4. CPU control by control memory using micro program.
General purpose register and cache design	5. Through most instruction are register based. So larger number of registers 32-192 are used and cache is split in data cache and instruction cache.	5. 8 to 34 general purpose register is present. Unified cache is used for instruction and data.